The present invention relates to the field of power MOS transistors and more particularly to power MOS transistors, formed according to the so-called N-channel DMOS (Diffused MOS) technology, which require, when their drain is connected to a supply source and their source is connected to a load, a gate voltage higher than the supply voltage. The case of power MOS transistors connected to inductive loads is more particularly considered.
FIG. 1 illustrates a first way of forming a circuit wherein an inductive load L is connected to the source SP of a power MOS transistor MP, the drain DP of which is connected to the first terminal 1 of the supply source, the free terminal of the load being connected to the second terminal 2 of this supply source. Terminal 1 of the supply source supplies a positive voltage VCC and terminal 2 is grounded.
A voltage booster circuit 3, internal to the circuit and supplying a voltage VH higher than the supply voltage VCC, is connected to the gate GP of the MOS transistor MP through a current source 4. The gate GP is further connected to the drain DP-1 of a DMOS transistor MP-1, the source SP-1 of which is connected to terminal 2 of the supply source and the gate GP-1 is connected to a control circuit 5.
Schematically, the control circuit 5 supplies at the gate GP-1 low level voltage signals and high level voltage signals for controlling transistor MP-1. In case of low level signals, MOS transistor MP-1 is blocked and MOS transistor MP is conductive.
When the signals applied on gate GP-1 switch from low level to high level, transistor MP-1 becomes conductive. This transistor absorbs the current from the current source 4. which causes MOS transistor MP to be blocked.
When the current of an inductive load is interruped, there occurs at tis terminals an overvoltage according to relation V =-Ldi/dt. The voltage on source SP of transistor MP tends to drop below the ground.
When transistor MP is switched off, it is desirable that the inductive load be discharged as fast as possible, that is, that quantity di/dt be as high as possible. Therefore, it is desired that the voltage on the transistor source substantially drop. On the other hand, if the source voltage drops, the gate voltage also drops while the difference between the gate and source voltages is equal to the threshold voltages V.sub.TP of transistor MP. But, a too low gate voltage would cause transistor to breakdown. One has thus provided for a clamping device 6 constituted by a set of n Zener diodes Z1, Z2, . . ., Zn in series wherein diode Z1 has its cathode 7 connected to the terminal 1 of the supply source and wherein diode Zn has its anode 8 connected to the gate of transistor MP. The voltage drop on the source of transistor MP is limited to a clamping voltage equal to VCC-(nV.sub.Z +V.sub.TP), where V.sub.Z is the Zener voltage of each of the Zener diodes Z1, Z2, . . ., Zn. The supply voltage VCC is for example 35 volts. The net voltage drop corresponding to the sum of n Zener voltages of diodes Z1, Z2, . . ., Zn is for example 50 volts. The threshold voltage V.sub.TP between the gate and source of MOS transistor MP is about 3 volts. Thus, the source voltage of transistor MP is liable to decrease down to a clamping voltage of about -20 volts.
The circuit of FIG. 1 is commonly implementable without difficulties. However, for the type of technology which is shown in FIGS. 2A and 2B, the DMOS transistor MP-1 prevents the voltage from dropping down to the clamping voltage.
FIG. 2A is a section view of a logic MOS transistor (portion I), an NPN bipolar transitor (portion II) and a portion of a power MOS transistor (portion III) with a technology capable of incorporating such transistors in the same integrated circuit chip. The components are formed on a P-type substrate 21.
In logic transistor I, two N-type diffusions 22, 23 are formed in a P-type box 24 for constituting the drain and source, respectively. The transistor gate 25 is located above a gate oxide layer 26. The P-type box 24 is in turn located in another N-type box 27 which is connected to the terminal of the supply source supplying the positive voltage VCC. The substrate is grounded.
The NPN bipolar transistor II comprises an emitter 31 constituted by an N-type diffusion in a P-type box 32 which forms the transistor base. The base contact is taken on an overdoped P.sup.30 region 33. The P-type box 32 is located in an N-type box 34 which constitutes the collector. Box 34 is in contact with an N.sup.30 -type buried layer 35 connected to a collector contact 36.
A DMOS transistor comprises a set of cells, one of which is shown in portion III of FIG. 2A. A cell comprises two regions 39-1, 39-2 constituted by P-type diffusions. In each region 39-1, 39-2 are formed two N-type diffusions 40 which constitute the power transistor source. The two diffusions 40 are interconnected through a conductive layer 41. The lateral edges of regions 39-1, 39-2 constitute the channel regions 42. Regions 39-1, 39-2 are positioned in an N-type box 43 forming the transistor drain. Box 43 contacts an N.sup.+ -type buried layer 44 connected to a drain contact 45. Each cell comprises a gate 46 located above a gate oxide layer 47.
FIG. 2B represents in portions I, II and III the symbols of the transistors shown in portions I, II and III of FIG. 2A, respectively. Near each transistor symbol is shown a diode present in the structure. Those diode symbols are also shown in the structures of FIG. 2A. In portion I, a diode 50 is formed between substrate 21 and the N-type box 27. Its anode is grounded and its cathode is connected to the terminal of the supply source which supplies voltage VCC. The structure of portion II exhibits a diode 51 between substrate 21 and the N.sup.+ -type buried layer 35. Its anode is grounded and its cathode is connected to the collector of the bipolar transistor. In portion III, a diode 52 is located between substrate 21 and the N.sup.+ -type buried layer 44. Its anode is grounded and its cathode is connected to the power transistor drain.
In FIG. 1, diode 52 in the DMOS transistor MP-1 is drawn in dotted lines. This diode 52 exhibits across its terminals a voltage drop V.sub.D when it is forward biased. Thus, at the switching off of MOS transistor MP, the voltage on source SP of this transistor MP cannot drop below the value -(V.sub.D +V.sub.TP), that is substantially -3.7 volts. The above mentioned clamping voltage, of about -20 volts, is not reached.
If a bipolar transistor is substituted for the DMOS transistor MP-1, the same problem is encountered due to the presence of diode 51.
The only type of transistor liable to replace DMOS transistor MP-1 is the logic MOS transistor. Diode 50 in this transistor does not impair the circuit operation.
Another way of forming a circuit wherein an inductive load L is fed through a power MOS transistor MP is shown in FIG. 3. In this circuit, transistor MP has its gate GP connected to drain DL of a logic MOS transistor ML. A voltage booster device 3 and a clamping device 6 are arranged in the same way as shown in FIG. 1.
A conventional control circuit 56 is shown in detail. It is fed by the circuit supply source. This allows the voltage booster device 3 to feed the gate of transistor MP only. The control circuit comprises a differential stage 59 formed by a current source 60, a reference voltage source 61 supplying a reference voltage V.sub.R and two MOS transistors MP-2 and MP-3 of the diffused-type comprising one cell. The gate of transistor MP-2 constitutes the input 62 of the control circuit. Transistors MP-2 and MP-3 are connected to current mirrors M2, M3, respectively, each of which is in turn comprised of a pair of P-channel MOS transistors arranged as shown in the figure. Current mirror M2 is connected to drain DA of a logic MOS transistor MA and current mirror M3 is connected to drain DB of a logic MOS transistor MB, transistors MA and MB being also arranged as a current mirror M in the way shown in the figure. Drain DB of transistor MB constitutes output 63 of the control circuit 56, this output being connected to gate GL of the logic MOS transistor ML.Sourches SA and SB of transistors MA and MB, respectively, are interconnected and connected to source SL of transistor ML through an auxiliary connection 64. The source of transistor ML is in turn connected to the source SP of transistor MP.
A control circuit such as circuit 56, with an appropriate supply, operates in the following way. When the voltage on input 62 of the control circuit is higher than the reference voltage V.sub.R, transistor MP-2 of the differential stage is conductive and transistor MP-3 is blocked. Since transistor MP-2 is conductive, the transistors of the current mirror M2, as well as the transistors of the current mirror M, are conductive. Conversely, since transistor MP-3 is blocked, the transistors of the current mirror M3 are blocked. The voltage at output 63 of the control circuit is set to low level to render transistor ML blocked and power MOS transistor MP conductive.
When the voltage at input 62 of the control circuit is lower than the reference voltage V.sub.R, transistor MP-2 and the transistors of cirrent mirrors M2 and M are blocked. Transistor MP-3 and the transistors of currrent mirror M3 are conductive. The voltage at output 63 of the control circuit is set to high level to render transistor ML conductive and transistor MP blocked.
In the type of technology implemented, transistors MA and MB are necessarily logic MOS transistors. Indeed, if DMOS transistors or bipolar transistors were used, diodes 52 or 51, respectively, would be formed (FIGS. 2A and 2B). If the substrate happened to be isolated from the ground, spurious pulses might be transmitted to the drains or collectors of those transistors through the diodes. This would especially impair the gate voltage of the logic MOS transistor ML.
The logic MOS transistors MA and MB, as well as logic MOS transistor ML, are positioned in an N-type box (box 27 in FIG. 2A) which is in turn connected to the supply source. The voltages at their sources, gates and drains may then decrease substantially below the voltage of the substrate which is grounded. Thus, the voltage at source SP of transistor MP is liable to decrease down to clamping voltage.
However, a problem is incountered in the phase where input 62 of the control circuit is set to high level to render power MOS transistor MP conductive. Indeed, in case such a power MOS transistor is conductive, the voltage drop between the drain and source is low, for example about 0.3 volt. The voltage at the sources SA and SB of transistors MA and MB, respectively, would then be equal to the supply voltage VCC minus 0.3 volt. On the other hand, it has been noted that the logic MOS transistors MA and MB were set to conductive state to render transistor MP also conductive. But, for a logic MOS transistor to be conductive, its drain voltage has to be higher than its source voltage by at least a threshold voltage V.sub.L which is about 1.5 volts. The voltage at the drains of the logic MOS transistors MA and MB has therefore to be substantially higher than the supply voltage VCC. Thus, since it is necessary to use logic MOS transistor for transistors MA and MB in the technology used and shown in FIGS. 2A and 2B, it is impossible to feed the control circuit with the supply source. The problem encountered is that it is impossible to control transistor ML with a control circuit connected to the supply source when input 62 is at high level to render transistor MP conductive.
The method which would consist in feeding the control circuit with the voltage booster circuit cannot be considered since this booster circuit already feeds the gate of the power MOS transistor MP and cannot withstand the additional load of the control circuit.